Senior FPGA Design Engineer

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.

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Equal Employment Opportunity

Draper is committed to creating a diverse environment and is proud to be an affirmative action and equal opportunity employer. We understand the value of diversity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, gender identity, national origin, veteran status, or genetic information.

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We are seeking a talented senior engineer to join the digital design team at Draper. The successful candidate will contribute to FPGA development including architecture, design, synthesis, verification, validation, test, and support. Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital FPGA efforts. Applicant should also be familiar with embedded software development for FPGA SoCs. Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware. Direct experience with embedded FPGA design is required.

Required Qualifications:

BSEE with 6+ years relevant experience
• Fluent in Verilog/VHDL
• Implementation of FPGA functions to accelerate SW (checksum engines, packet parsing, etc.)
• Experience with Microchip Libero tools, PolarFire (SoC) devices, and IP
• Experience with Xilinx Vivado tools, devices, and IP
• Experience with joint design/debug with embedded software
• Experience debugging FPGA fabric designs with embedded processor software on HW
• Capability for evaluating trade space for adding new features to FPGA fabric and/or software (knows strengths of each technology and can optimize based on requirements)
• Experience with design closure including timing, power and area for SWaP constrained designs
• Experience with DSP implementation in FPGA
• Familiarity with high speed interfaces (10Gbit Ethernet, PCIe, DDR4, LVDS, etc)
• Experience with Linux and scripting languages
• Strong analysis and problem solving skills
• Minimum of 3 days onsite in Cambridge is required

Preferred Qualifications:

• MSEE with 6+ years relevant experience
• Understanding of networking layered models and protocols
• Experience with 10GB Ethernet and IP id HDL designs
• Experience with Matlab/Simulink
• Experience working with PCB designers

Security Requirement:

Current in scope DoD Secret clearance required. Strong preference will be given to candidates with a current in scope DoD Top Secret clearance.

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